AD9773EB datasheet(13/19 Pages) AD

13 / 19 page

AD9773

PRELIMINARY TECHNICAL DATA

N 1

N 0

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

Serial Interface For Register Control

The AD9773 serial port is a flexible, synchronous serial

communications port allowing easy interface to many

industry standard microcontrollers and microprocessors.

The serial I/O is compatible with most synchronous

transfer formats, including both the Motorola SPI and

Intel SSR protocols. The interface allows read/write

access to all registers that configure the AD9773. Single

or multiple byte transfers are supported as well as MSB

first or LSB first transfer formats. The AD9773’s serial

interface port can be configured as a single pin I/O

(SDIO) or two unidirectional pins for in/out (SDIO/

SDO).

General Operation of the Serial Interface

There are two phases to a communication cycle with

the AD9773. Phase 1 is the instruction cycle, which is

the writing of an instruction byte into the AD9773,

coincident with the first eight SCLK rising edges. The

instruction byte provides the AD9773 serial port con-

troller with information regarding the data transfer

cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the up-

coming data transfer is read or write, the number of

bytes in the data transfer and the starting register ad-

dress for the first byte of the data transfer. The first

eight SCLK rising edges of each communication cycle

are used to write the instruction

byte into the

AD9773.

A logic high on the CS pin, followed by a logic low,

will reset the SPI port timing to the initial state of the

instruction cycle. This is true regardless of the present

state of the internal registers or the other signal levels

present at the inputs to the SPI port. If the SPI port is

in the midst of an instruction cycle or a data transfer

cycle, none of the present data will be written.

The remaining SCLK edges are for Phase 2 of the

communication cycle. Phase 2 is the actual data transfer

between the AD9773 and the system controller. Phase 2

of the communication cycle is a transfer of 1, 2, 3, or 4

data bytes as determined by the instruction byte. Nor-

mally, using one multibyte transfer is the preferred

method. However, single byte data transfers are useful to

reduce CPU overhead when register access requires one

byte only. Registers change immediately upon writing to the

last bit of each transfer byte.

Instruction Byte

The instruction byte contains the following information

as shown below:

Figure 3. AD9773 SPI Port Interface

R/W- bit 7 of the instruction byte determines whether a

read or a write data transfer will occur after the instruction

byte write. Logic high indicates read operation . Logic

zero indicates a write operation. N1, N0 -Bits 6 and 5 of

the instruction byte determine the number of bytes to be

transferred during the data transfer cycle. The bit decodes

are shown in the following table:

A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte

determine which register is accessed during the data

transfer portion of the communications cycle. For multibyte

transfers, this address is the starting byte address. The

remaining register addresses are generated by the AD9773.

Serial Interface Port Pin Description

SCLK (pin55) - Serial Clock. The serial clock pin is used

to synchronize data to and from the AD9773 and to run

the internal state machines. SCLK maximum frequency

is 15 MHz. All data input to the AD9773 is registered on

the rising edge of SCLK. All data is driven out of the

AD9773 on the falling edge of SCLK.

CSB (pin 56) - Chip Select. Active low input starts and

gates a communication cycle. It allows more than one

device to be used on the same serial communications

lines. The SDO and SDIO pins will go to a high

impedance state when this input is high. Chip select

should stay low during the entire communication cycle.

SDIO (pin 54) - Serial Data I/O. Data is always written

into the AD9773 on this pin. However, this pin can be

used as a bidirectional data line. The configuration of this

pin is controlled by Bit 7 of register address 00h. The

default is logic zero, which configures the SDIO pin as

unidirectional.

SDO(pin 53) - Serial Data Out. Data is read from this pin

for protocols that use separate lines for transmitting and

receiving data. In the case where the AD9773 operates in

a single bidirectional I/O mode, this pin does not output

data and is set to a high impedance state.

MSB/LSB Transfers

The AD9773 serial port can support both most signifi-

cant bit (MSB) first or least significant bit (LSB) first

data formats. This functionality is controlled by register

address 00h bit 6. The default is MSB first. When this bit

is set active high, the AD9773 serial port is in LSB first

AD9773 SP I P or t

Inter face

SCLK (pin 55)

CSB (pin 56)

SDIO (pin 54)

SDO (pin 53)

REV. PrA

AD9773EB Scheda tecnica(PDF) 13 Page - Analog Devices

AD9773EB Scheda tecnica(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Scheda tecnica Scarica

Link URL