AD9826

–10–

REV. A

PIXEL n (R,G,B)

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

R (n–1)

HIGH

BYTE

LOW

BYTE

HB

LB

HB

HB

HB

HB

HB

LB

LB

LB

LB

LB

R (n–2)

G (n–2)

G (n–2)

B (n–2)

B (n–2)

R (n–1)

G (n–1)

G (n–1)

B (n–1)

B (n–1)

R (n)

R (n)

G (n)

G (n)

PIXEL (n+1)

Figure 5. 3-Channel SHA Mode Timing

HIGH BYTE

LOW BYTE

LOW BYTE

LOW BYTE

HIGH BYTE

HIGH BYTE

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

PIXEL n

PIXEL (n–4)

PIXEL (n–4)

PIXEL (n–3)

PIXEL (n–3)

PIXEL (n–2)

PIXEL (n–2)

NOTE

IN 1-CHANNEL SHA MODE,THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”

Figure 6. 1-Channel SHA Mode Timing