AD9831AST datasheet(3/16 Pages) AD

3 / 16 page

AD9831

–3–

REV. A

TIMING CHARACTERISTICS (V

DD = +3.3 V

10%, +5 V

10%; AGND = DGND = 0 V, unless otherwise noted)

Limit at

TMIN to TMAX

Parameter

(A Version)

Units

Test Conditions/Comments

ns min

MCLK Period

ns min

MCLK High Duration

ns min

MCLK Low Duration

t4*

ns min

Rising Edge to MCLK Rising Edge

t4A*

ns min

Rising Edge After MCLK Rising Edge

ns min

Pulse Width

ns min

Duration between Consecutive WR Pulses

ns min

Data/Address Setup Time

ns min

Data/Address Hold Time

t9*

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

t9A*

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

t10

ns min

RESET

Pulse Duration

*See Pin Description section.

Guaranteed by design but not production tested.

MCLK

Figure 2. Clock Synchronization Timing

A0, A1, A2

DATA

VALID DATA

Figure 3. Parallel Timing

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

RESET

Figure 4. Control Timing

AD9831AST Scheda tecnica(PDF) 3 Page - Analog Devices

AD9831AST Scheda tecnica(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL