AD9854SLASHPCB datasheet(36/44 Pages) AD

36 / 44 page

AD9854

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Observing the Unﬁltered IOUT1 and the Unﬁltered IOUT2

DAC Signals

This allows the viewer to observe the unﬁltered DAC outputs at

J2 (the “I” signal) and J1 (the “Q” signal). The procedure below

simply routes the two 50

Ω terminated analog DAC outputs to

the BNC connectors and disconnects any other circuitry. The

“raw” DAC outputs will be a series of quantized (stepped) output

levels. The default 10 mA output current will develop a 0.5 V p-p

signal across the on-board 50

Ω termination. When connected

to an external 50

Ω input, the DAC will therefore develop 0.25 V p-p

due to the double termination.

1. Install shorting jumpers at W7 and W10.

2. Remove shorting jumper at W16.

3. Remove shorting jumper from 3-pin header W1.

4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W4.

Observing the Filtered IOUT1 and the Filtered IOUT2

This allows viewer to observe the ﬁltered I and Q DAC outputs

at J4 (the “I” signal) and J3 (the “Q” signal). This places the

Ω (input and output Z) low-pass ﬁlters in the I and Q DAC

pathways to remove images and aliased harmonics and other

spurious signals above the dc to approximately 120 MHz band-

pass. These signals will appear as nearly pure sine waves and

exactly 90 degrees out-of-phase with each other. These ﬁlters

are designed with the assumption that the system clock speed is

at or near maximum (300 MHz). If the system clock utilized is

much less than 300 MHz, for example 200 MHz, unwanted DAC

products other than the fundamental signal will be passed by the

low-pass ﬁlters.

1. Install shorting jumpers at W7 and W10.

2. Install shorting jumper at W16.

3. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W1.

4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of

3-pin header W4.

5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-

pin header W2 and W8.

Observing the Filtered IOUT and the Filtered IOUTB

This allows viewer to observe only the ﬁltered “I” DAC outputs

at J4 (the “true” signal) and J3 (the “complementary” signal).

This places the 120 MHz low pass ﬁlters in the true and comple-

mentary output paths of the I DAC to remove images and aliased

harmonics and other spurious signals above approximately

120 MHz. These signals will appear as nearly pure sine waves

and exactly 180 degrees out-of-phase with each other. Again, if

the system clock used is much less than 300 MHz, for example

200 MHz, then unwanted DAC products other than the funda-

mental signal will be passed by the low-pass ﬁlters.

1. Install shorting jumpers at W7 and W10.

2. Install shorting jumper at W16.

3. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-

pin header W1.

4. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-

pin header W4.

5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-

pin header W2 and W8.

To connect the high-speed comparator to the DAC output sig-

nals choose either the quadrature ﬁltered output conﬁguration

or the complementary ﬁltered output conﬁguration as outlined

above. Follow Steps 1 through 4 above, for the desired ﬁltered

conﬁguration. Step 5 below will reroute the ﬁltered signals away

from their connectors (J3 and J4) and connect them to the 100

Ω

conﬁgured comparator inputs. This conﬁgures the comparator

for differential input without control of the comparator output

duty cycle. The comparator output duty cycle should be approxi-

mately 50% in this conﬁguration.

5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of

3-pin header W2 and W8.

User may elect to change the RSET resistor, R2 from 3.9 k

Ω to

2 k

Ω to get a more robust signal at the comparator inputs. This

will decrease jitter and extend comparator operating range. This

can be accomplished by soldering a second 3.9 k

Ω chip resistor

in parallel with the provided R2.

Connecting the High-Speed Comparator in a Single-Ended

Conﬁguration

This will allow duty cycle or pulse width control and requires that a

dc threshold voltage be present at one of the comparator inputs.

You may supply this voltage using the “Q DAC” by conﬁguring

it as a control DAC in software or by removing the shorting jumper

at 2-pin header W6. A 12-bit, twos-complement value is written

to the Q-DAC register that will set the IOUT2 output to a static

dc level. Allowable hexadecimal values are 7FF (maximum) to

800 (minimum) with all 0s being midscale. The IOUT1 channel

will continue to output a ﬁltered sine wave programmed by the

user. These two signals are routed to the comparator inputs

using W2 and W8 3-pin header switches. The conﬁguration

described above entitled “Observing the Filtered IOUT and the

Filtered IOUTB” must be used. Follow Steps 1 through 4 and

then the following Step 5:

5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of

3-pin header W2 and W8.

User should elect to change the RSET resistor from 3900

Ω to

1950

Ω to get a more robust signal at the comparator inputs.

This will decrease jitter and extend comparator operating range.

User can accomplish this by soldering a second 3.9 k

Ω chip

resistor in parallel with the provided R2.

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