AD9888SLASHPCB datasheet(20/32 Pages) AD

20 / 32 page

REV. A

AD9888

–20–

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP

IDENTIFICATION

7-0

Chip Revision

An 8-bit register that represents the silicon revision.

Revision 0 = 0000 0000, Revision 1 = 0000 0001.

PLL DIVIDER CONTROL

7-0

PLL Divide Ratio MSBs

The eight most significant bits of the 12-bit PLL divide ratio

PLLDIV. (The operational divide ratio is PLLDIV + 1.)

The PLL derives a master clock from an incoming Hsync

signal. The master clock frequency is then divided by an

integer value, such that the output is phase-locked to Hsync.

This PLLDIV value determines the number of pixel times

(pixels plus horizontal blanking overhead) per line. This is

typically 20% to 30% more than the number of active pixels

in the display.

The 12-bit value of the PLL divider supports divide ratios

from 2 to 4095. The higher the value loaded in this regis-

ter, the higher the resulting clock frequency with respect

to a fixed Hsync frequency.

VESA has established standard timing specifications, which

will assist in determining the value for PLLDIV as a func-

tion of horizontal and vertical display resolution and frame

rate (Table IV).

However, many computer systems do not conform pre-

cisely to the recommendations, and these numbers should

be used only as a guide. The display system manufacturer

should provide automatic or manual means for optimizing

PLLDIV. An incorrectly set PLLDIV will usually produce

one or more vertical noise bars on the display. The greater

the error, the greater the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69h, PLLDIVL = Dxh).

The AD9888 updates the full divide ratio only when the

LSBs are changed. Writing to this register by itself will

not trigger an update.

7-4

PLL Divide Ratio LSBs

The four least significant bits of the 12-bit PLL divide

ratio PLLDIV. The operational divide ratio is PLLDIV + 1.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69h, PLLDIVL = Dxh).

The AD9888 updates the full divide ratio only when this

CLOCK GENERATOR CONTROL

7-6

VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the desired

operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high fre-

quencies. For this reason, in order to output low pixel

rates and still get good jitter performance, the PLL actu-

ally operates at a higher frequency but then divides down

the clock rate afterwards. Table VI shows the pixel rates

for each VCO range setting. The PLL output divisor is

automatically selected with the VCO range setting.

Table VI. VCO Ranges

VCORNGE

Pixel Rate Range

10–45

45–90

90–150

150+

The power-up default value is 01.

5-3

Charge Pump Current

Three bits that establish the current driving the loop filter

in the clock generator.

Table VII. Charge Pump Currents

CURRENT

Current ( A)

000

001

100

010

150

011

250

100

350

101

500

110

750

111

1500

CURRENT must be set to correspond with the desired

operating frequency (incoming pixel rate).

The power-up default value is CURRENT = 001.

7-3

Clock Phase Adjust

A five-bit value that adjusts the sampling phase in 32 steps

across one pixel time. Each step represents an 11.25

° shift

in sampling phase.

The power-up default value is 16.

CLAMP TIMING

7-0

Clamp Placement

An 8-bit register that sets the position of the internally

generated clamp.

When the external clamp control bit is set to 0, a clamp

signal is generated internally, at a position established by

the clamp placement and for a duration set by the clamp

duration. Clamping is started (Clamp Placement) pixel

periods after the trailing edge of Hsync. The clamp place-

ment may be programmed to any value up to 255, except 0.

The clamp should be placed during a time that the input

signal presents a stable black-level reference, usually the

back porch period between Hsync and the image.

When the external clamp control bit is set to 1, this regis-

ter is ignored.

7-0

Clamp Duration

An 8-bit register that sets the duration of the internally

generated clamp.

When the external clamp control bit is set to 0, a clamp

signal is generated internally, at a position established by

the clamp placement and for a duration set by the clamp

duration. Clamping is started (Clamp Placement) pixel

periods after the trailing edge of Hsync, and continues for

(Clamp Duration) pixel periods. The clamp duration may

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