REV. B

ADC912A

–11–

MICROPROCESSOR INTERFACING

The ADC912A has self-contained logic for both 8-bit and 16-bit

data bus interfacing. The output data can be formatted into

either a 12-bit parallel word for a 16-bit data bus or an 8-bit

data word pair for an 8-bit data bus. Data is always right justi-

fied, i.e., LSB is the most right-hand bit in a 16-bit word. For a

selection is governed by the HBEN input which controls an

internal digital multiplexer. This multiplexes the 12 bits of

8 LSBs) where it can be read in two read cycles. The 4 MSBs

drivers are turned on. See Figure 20.

Two A/D conversion modes of operation are available for both

data bus sizes: the ROM mode and the Slow-Memory mode.

DQ

"1"

ACTIVE HIGH

(HBEN = "0")

CONVERSION START

(POSITIVE EDGE

TRIGGER)

ACTIVE HIGH

(HBEN = "1")

ENABLE THREE-STATE

OUTPUTS

DATA BITS: LOGIC LOW

ENABLE THREE-STATE

OUTPUTS

HBEN

ADC912A

CS

RD

BUSY

CLR

Figure 20. Internal Logic for Control Inputs

CS, RD, and

HBEN

In the ROM mode each READ instruction obtains new, valid

data, assuming the minimum timing requirements are satisfied.

However, since the data output from a current READ instruc-

tion was generated from a conversion initiated by a previous

READ operation, the current data may be out-of-date. To be

sure of obtaining up-to-date data, READ instructions may be

coded in pairs (with some NOPs between them); use only the

data from the second READ in each pair. The first READ starts

the conversion, the second READ gets the results.

The Slow-Memory mode is the simplest. It is the method of

choice where compact coding is essential, or where software

bugs are a hazard. In this mode, a single READ instruction will

initiate a data conversion, interrupt the microprocessor until

completion (WAIT states are introduced), then read the results.

If the system throughput tolerates WAIT states, and the hardware

is correct, then the Slow-Memory mode is virtually immune to

subsequent software modifications. Placing the microprocessor

in the WAIT state has an additional advantage of quieting the

digital system to reduce noise pickup in the analog conversion

circuitry. The 12-bit parallel Slow-Memory mode provides the

fastest analog sampling rate combined with digital data transfer

rate for sampled-data systems.

PARALLEL READ, SLOW-MEMORY MODE

(HBEN = LOW)

Figure 5 shows the timing diagram and data bus status for Par-

allel Read, Slow-Memory Mode.

CS and RD going low triggers

a conversion and the ADC912A acknowledges by taking

BUSY

low. Data from the previous conversion appears on the three-

state data outputs.

BUSY returns high at the end of conversion,

when the output latches have been updated, and the conversion

TWO-BYTE READ, SLOW-MEMORY MODE

are used. Conversion start procedure and data output status for

the first read operation is identical to Parallel Read, Slow-Memory

Mode. See Figure 6, Timing Diagram and Data Bus Status. At

from the A/D converter. A second READ operation with HBEN

disables conversion start. Note the 4 MSBs also appear on data

PARALLEL READ, ROM MODE (HBEN = LOW)

A conversion is started with a READ operation. The 12 bits of

data from the previous conversion are available on data outputs

not required. A second READ operation reads the new data

as long as the ADC912A conversion time must be allowed be-

tween READ operations. If a READ takes place prior to the end

of 13 CLKS of the ADC conversion, the remaining bits not yet

tested will be invalid.

TWO-BYTE READ, ROM MODE

Conversion is started in the same way with a READ operation

and the data output status is the same as the Parallel Read,

ROM Mode. See Figure 8, Two-Byte Read Timing Diagram,

ROM Mode. Two more READ operations are required to obtain

the new conversion result. A delay equal to the ADC912A con-

version time must be allowed between conversion start and

and starts another conversion. The 4 MSBs also appear on data