OPTION_REG datasheet(159/222 Pages) MICROCHIP

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DS22331A-page 159

MCP19111

27.4.4.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPCON3 register

enables additional clock stretching and interrupt

generation after the 8th falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPIF

interrupt is set.

Figure 27-11 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

Bus starts Idle.

Master sends Start condition; the S bit of

SSPSTAT is set; SSPIF is set if interrupt on Start

detect is enabled.

Master sends matching address with R/W bit

set. After the 8th falling edge of the SCL line, the

CKP bit is cleared and SSPIF interrupt is

generated.

Slave software clears SSPIF.

Slave software reads ACKTIM bit of SSPCON3

Slave reads the address value from the

SSPBUF register clearing the BF bit.

Slave software decides from this information if it

wishes to ACK or not ACK and sets ACKDT bit

of the SSPCON2 register accordingly.

Slave sets the CKP bit releasing SCL.

Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPIF.

12. Slave loads value to transmit to the master into

SSPBUF setting the BF bit.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the 9th SCL pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPCON2 register.

16. Steps 10–15 are repeated for each byte

transmitted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: SSPBUF cannot be loaded until after the

ACK.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCL

line to receive a Stop.

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