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RT8015D Scheda tecnica(PDF) 3 Page - Richtek Technology Corporation |
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RT8015D Scheda tecnica(HTML) 3 Page - Richtek Technology Corporation |
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3 / 14 page ![]() RT8015D 3 DS8015D-02 March 2011 www.richtek.com Function Block Diagram Layout Guide Driver NISEN Control Logic NMOS I Limit 0.9V 0.7V 0.2V OC Limit ISEN Slope Com OSC Output Clamp EA 0.8V Int-SS POR OTP VREF COMP SHDN/RT GND FB PVDD VDD PGND SD LX PGOOD VIN GND L1 VOUT GND CIN COUT VOUT CCOMP R2 R1 CF ROSC Place the input and output capacitors as close to the IC as possible. LX should be connected to Inductor by wide and short trace, keep sensitive components away from this trace Place the feedback and compensation components as close to the IC as possible. RT8015D SHDN/RT GND PGND LX COMP FB PGOOD VDD PVDD LX 4 3 2 6 7 8 9 10 5 1 RCOMP R4 R3 C1 GND Bottom Layer |
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