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TLC5949PWPR Scheda tecnica(PDF) 11 Page - Texas Instruments |
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TLC5949PWPR Scheda tecnica(HTML) 11 Page - Texas Instruments |
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11 / 51 page ![]() Power-Save Mode SIN LAT Second Grayscale Data Latch (Internal) Previous On/Off Data SCLK 1 2 3 191 192 193 1 2 3 4 5 6 ¼ All Data Are '0' Low Power-Save Mode Normal Mode Normal Mode Normal Mode '1' PSMODE Bit In Control Data Latch (Internal) 001b OFF OUT0 7 8 15 , OUT , OUT , OUT OFF OUT1 6 9 14 , OUT , OUT , OUT OFF ICC (VCC Current) More Than 100 A m Less Than 100 A m t D6 t D7 BLANK Bit In Control Data Latch (Internal) ON or OFF ON or OFF ON or OFF ON ON ON OFF OUT2 5 10 13 , OUT , OUT , OUT ON or OFF ON OUT3 4 11 12 , OUT , OUT , OUT First Grayscale Data Latch (Internal) Previous On/Off Data All Data Are ‘0' ON or OFF ON or OFF ON or OFF ON or OFF First and second GS data latches are changed simultaneously because the BLANK bit is '1'. TLC5949 www.ti.com SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012 Figure 10. Power-Save Mode Timing Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TLC5949 |
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