OP176

REV. 0

–3–

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±22 V

Input Voltage

±18 V

Differential Input Voltage

±7.5 V

Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite

Storage Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Operating Temperature Range

OP176G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

Junction Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

°C

Package Type

θ

JA

3

θ

JC

Units

8-Pin Plastic DIP (P)

103

43

°C/W

8-Pin SOIC (S)

158

43

°C/W

NOTES

otherwise noted.

±7.5 V limit input current to less than 5 mA.

3

θ

for P-DIP packages;

θ

package.

(@ V

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the OP176 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

V

OS

1

mV max

Input Bias Current

I

B

V

350

nA max

Input Offset Current

I

OS

V

±50

nA max

Input Voltage Range

1

V

CM

±10.5

V min

Common-Mode Rejection

CMRR

V

80

dB min

Power Supply Rejection Ratio

PSRR

V =

±4.5 V to ±18 V

86

dB min

Large Signal Voltage Gain

A

VO

R

250

V/mV min

Output Voltage Range

V

O

R

13.5

V min

V

14.8

V min

Supply Current

I

SY

V

2.75

mA max

V

2.5

mA max

V

NOTES

Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

OP176 Die Size 0.069

× 0.067 Inch, 4,623 Sq. Mils.

Substrate (Die Backside) Is Connected to V–.

Transistor Count, 26.

WAFER TEST LIMITS

NULL

OUT

NULL

–IN

+IN

DICE CHARACTERISTICS

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

OP176GP

–40

°C to +85°C

8-Pin Plastic DIP

N-8

OP176GS

–40

°C to +85°C

8-Pin SOIC

SO-8

OP176GSR

–40

°C to +85°C

SO-8 Reel, 2500 Pieces

OP176GBC

+25

°C

DICE