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OP221GS Scheda tecnica(PDF) 4 Page - Analog Devices

Il numero della parte OP221GS
Spiegazioni elettronici  Dual Low Power Operational Amplifier, Single or Dual Supply
PDF  12 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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OP221GS Scheda tecnica(HTML) 4 Page - Analog Devices

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REV. A
–4–
OP221–SPECIFICATIONS
.
OP221A/E
OP221G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset
Voltage Match
∆V
OS
100
400
400
800
µV
Average Noninverting IB+VCM = 0
100
140
nA
Bias Current
Input Offset
IC
∆V
OS
12
3
5
µV°C
Voltage Tracking
Noninverting Input
IOS+VCM = 0
3
7
6
12
nA
Offset Current
Common-Mode
Rejection Ratio
∆CMRR VCM = –15 V to 13.2 V
87
90
72
80
dB
Match (Note 1)
Power Supply
Rejection Ratio
∆PSRR
26
140
µV/V
Match (Note 1)
NOTES
1
∆CMRR is 20 log10 VCM/∆CME, where VCM is the voltage applied to both noninverting inputs and ∆CME is the difference in common-mode input-referred error.
2
∆PSRR is: Input-Referred Differential Error
∆VS
(Matching Characteristics at Vs =
15 V, –55 C
≤ TA ≤ +125 C for OP221A,
–25 C
≤ TA ≤ +85 C for OP221E, –40 C ≤ TA ≤ +85 C for OP221G, unless otherwise noted.
Grades E and G are sample tested.)
.
OP221N
Parameter
Symbol
Conditions
Limit
Unit
Input Offset Voltage
VOS
200
µV Max
Input Offset Current
IOS
VCM = 0
3.5
nA Max
Input Bias Current
IB
VCM = 0
85
nA Max
Input Voltage Range
IVR
V+ = 5 V, V– = 0 V
0/3.5
V Min/Max
VS=
±15 V
–15/13.5
V Min
Common-Mode
CMRR
V– = 0 V, V+ = 5 V,
88
Rejection Ratio
0 V
≤ V
CM
≤ 3.5 V
VS =
±15 V
dB Min
–15 V
≤ VCM ≤ 13.5 V
93
Power Supply
PSRR
VS =
±2.5 V to ± 15 V
12.5
Rejection Ratio
V– = 0 V, V+ = 5 V to 30 V
22.5
V/mV Min
Large-Signal
Avo
VS =
±15 V
1500
Voltage Gain
RL = 10 k
V/mV Max
Output Voltage Swing
VO
V+ = 5 V, V– = 0 V, RL= 10 k
0.7/4.1
V Min/Max
VS = 15 V, RL = 10 k
Ω±13.8
V Min
Supply Current
ISY
VS =
±2.5 V, No Load
560
µA Max
(Both Amplifiers)
VS =
±15 V, No Load
810
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Wafer Test Limits at Vs =
2.5 V to
15 V, TA = 25 C, unless otherwise noted.



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