REV. A

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a

PKD01

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

Monolithic Peak Detector

with Reset-and-Hold Mode

FUNCTIONAL BLOCK DIAGRAM

–

+

PKD01

OUTPUT

BUFFER

OUTPUT

LOGIC

GND

DET

–IN

+IN

–IN

+IN

RST

–IN

+IN

OUTPUT

V+

V–

–

+

–

+

–

+

CMP

A

B

C

V–

GATED

AMP

GATED

AMP

RST

0

0

1

1

DET

0

1

1

0

OPERATIONAL MODE

PEAK DETECT

PEAK HOLD

RESET

INDETERMINATE

SWITCHES SHOWN FOR:

RST = “0,”

DET = “0”

FEATURES

Monolithic Design for Reliability and Low Cost

High Slew Rate: 0.5 V/ s

Low Droop Rate

Low Zero-Scale Error: 4 mV

Digitally Selected Hold and Reset Modes

Reset to Positive or Negative Voltage Levels

Logic Signals TTL and CMOS Compatible

Uncommitted Comparator On-Chip

Available in Die Form

GENERAL DESCRIPTION

The PKD01 tracks an analog input signal until a maximum

amplitude is reached. The maximum value is then retained as a

peak voltage on a hold capacitor. Being a monolithic circuit, the

PKD01 offers significant performance and package density

advantages over hybrid modules and discrete designs without

sacrificing system versatility. The matching characteristics

attained in a monolithic circuit provide inherent advantages

when charge injection and droop rate error reduction are

primary goals.

Innovative design techniques maximize the advantages of mono-

over conventional voltage amplifier circuit building blocks. The

acquisition time and maximize circuit accuracy. Their outputs

are easily switched by low glitch current steering circuits. The

steered outputs are clamped to reduce charge injection errors

upon entering the hold mode or exiting the reset mode. The inher-

ently low zero-scale error is further reduced by active Zener-Zap

trimming to optimize overall accuracy.

The output buffer amplifier features an FET input stage to

reduce droop rate error during lengthy peak hold periods. A bias

current cancellation circuit minimizes droop error at high ambi-

ent temperatures.

Through the

DET control pin, new peaks may either be detected

or ignored. Detected peaks are presented as positive output

levels. Positive or negative peaks may be detected without

additional active circuits, since Amplifier A can operate as an

inverting or noninverting gain stage.

An uncommitted comparator provides many application options.

Status indication and logic shaping/shifting are typical examples.