Aeroflex Circuit Technology

30

SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

A02

A01

A00

SSFLAG, SSBUSY, SVCRQST

DBAC, RTU/BC, MT, CTLIN B/A

MEM/REG

D15-D00

IOEN

SELECT

STRBD

(Internal)

16MHz Clock

RD/WR

READYD

See Note 1

DATA VALID

td1

tpw1

td2

td6

Figure 33 – CPU Reads from Internal Register Timing

CPU Reads from Internal Register

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

-

200

ns

td2

IOEN high delay (CPU Handshake)

-

20

ns

tpw1

READYD pulse width (CPU Handshake)

70

-

ns

td6

Internal Register delay (read)

-

60

ns

tr

READYD to STRBD release

-

1.37

µs

tz

-

1.8

µs

See Note 2

tz

tr

NOTE:

1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.