Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

21

A02 (38)

A01 (77)

A00 (39)

MEM/REG (10)

D15-D00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

td9

tpw1

DATA FROM EXTERNAL REGISTER

EXTEN (4)

td2

Figure 23 – CPU reads from external register

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Reads from External Register Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

-

200

ns

td2

IOEN high delay (CPU Handshake)

-

20

ns

tpw1

READYD pulse width (CPU Handshake)

70

-

ns

td9

Register Data/Address set-up time

-

40

ns