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74ACT715-RSC Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor |
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74ACT715-RSC Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor |
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5 / 14 page ![]() 5 www.fairchildsemi.com FIGURE 2. Vertical Waveform Specification FIGURE 3. Equalization/Serration Interval Programming HORIZONTAL AND VERTICAL GATING SIGNALS Horizontal Drive and Vertical Drive outputs can be utilized as general purpose Gating Signals. Horizontal and Vertical Gating Signals are available for use when Composite Sync and Blank signals are selected and the value of Bit 2 of the Status Register is 0. The Vertical Gating signal will change in the same manner as that specified for the Vertical Blank. Horizontal Gating Signal Width = [REG(16) − REG(15)] × ckper Vertical Gating Signal Width: = [REG(18) − REG(17)] × hper CURSOR POSITION AND VERTICAL INTERRUPT The Cursor Position and Vertical Interrupt signal are avail- able when Composite Sync and Blank signals are selected and Bit 2 of the Status Register is set to the value of 1. The Cursor Position generates a single pulse of n clocks wide during every line that the cursor is specified. The signals are generated by logically ORing (ANDing) the active LOW (HIGH) signals specified by the registers used for generat- ing Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical inter- val specified. The Vertical Interrupt signal will change in the same manner as that specified for the Vertical Blanking sig- nal. Horizontal Cursor Width = [REG(16) − REG(15)] × ckper Vertical Cursor Width = [REG(18) − REG(17)] × hper Vertical Interrupt Width = [REG(14) − REG(13)] × hper |
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