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LSM330DLCTR Scheda tecnica(PDF) 23 Page - STMicroelectronics

Il numero della parte LSM330DLCTR
Spiegazioni elettronici  iNEMO inertial module: 3D accelerometer and 3D gyroscope
PDF  66 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
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LSM330DLCTR Scheda tecnica(HTML) 23 Page - STMicroelectronics

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LSM330DLC
Functionality
Doc ID 022162 Rev 2
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4.4
FIFO
The LSM330DLC embeds 32 slots of 16-bit data FIFO for each of the three output channels:
yaw, pitch and roll. This allows consistent power saving for the system, since the host
processor does not need to continuously poll data from the sensor, but can wake up only
when needed and burst the significant data out from the FIFO. This buffer can work
accordingly in five different modes: Bypass mode, FIFO mode, Stream mode, Bypass-to-
Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits in
the FIFO_CTRL_REG_G register. Programmable watermark level, FIFO_empty or
FIFO_Full events can be enabled to generate dedicated interrupts on the DRDY_G/INT2_G
pin (configured through the CTRL_REG3_G register and event detection information is
available in the FIFO_SRC_REG_G register. Watermark level can be configured to WTM4:0
in the FIFO_CTRL_REG_G register.
4.4.1
Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. As
described in Figure 6 below, for each channel only the first address is used. The remaining
FIFO slots are empty. When new data is available the old data is overwritten.
Figure 6.
Bypass mode
4.4.2
FIFO mode
In FIFO mode, data from the yaw, pitch and roll channels is stored in the FIFO. A watermark
interrupt can be enabled (I2_WMK bit in the CTRL_REG3_G register) in order to be raised
when the FIFO is filled to the level specified in the WTM 4:0 bits of the FIFO_CTRL_REG_G
register. The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch and
roll). When full, the FIFO stops collecting data from the input channels. To restart data
collection, the FIFO_CTRL_REG_G register must be written back to Bypass mode.
FIFO mode is represented in Figure 7: FIFO mode.
x0
y
z0
y0
x1
y1
z1
x2
y2
z2
x31
y31
z31
xi,yi,zi
empty
AM07231v1



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