MT9P031 datasheet(21/46 Pages) ETC1

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MT9P031_DS - Rev. F 5/11 EN

MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor

Features

Reset

The MT9P031 may be reset by using RESET_BAR (active LOW) or the reset register.

Hard Reset

Assert (LOW) RESET_BAR, it is not necessary to clock the device. All registers return to

the factory defaults. When the pin is negated (HIGH), the chip resumes normal opera-

tion.

Soft Reset

Set the Reset register field to “1” (R0x0D[0] = 1). All registers except the following will be

reset:

•Chip_Enable

• Synchronize_Changes

•Reset

• Use_PLL

•Power_PLL

• PLL_m_Factor

• PLL_n_Divider

•PLL_p1_Divider

When the field is returned to “0,” the chip resumes normal operation.

Power Up and Power Down

When first powering on the MT9P031, follow this sequence:

1. Ensure RESET_BAR is asserted (LOW).

2. Bring up the supplies. If both the analog and the digital supplies cannot be brought

up simultaneously, ensure the digital supply comes up first.

3. Negate RESET_BAR (HIGH) to bring up the sensor.

When powering down, be sure to follow this sequence to ensure that I/Os do not load

any buses that they are connected to.

1. Assert RESET_BAR.

2. Remove the supplies.

Clocks

The MT9P031 requires one clock (EXTCLK), which is nominally 96 MHz. By default, this

results in pixels being output on the DOUT pins at a maximum data rate of 96 Mp/s. With

VDD_IO = 1.8V, maximum master clock and maximum data rate become 48 MHz and

48 Mp/s, respectively. The EXTCLK clock can be divided down internally by setting

Divide_Pixel_Clock to a non-zero value. This slows down the operation of the chip as

though EXTCLK had been divided externally.

fEXTCLK

if Divide_Pixel_Clock = 0

fPIXCLK= {

fEXTCLK / (2 × Divide_Pixel_Clock)

otherwise

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