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STM32F415VG Scheda tecnica(PDF) 117 Page - STMicroelectronics |
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STM32F415VG Scheda tecnica(HTML) 117 Page - STMicroelectronics |
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117 / 186 page  DocID022063 Rev 4 117/186 STM32F415xx, STM32F417xx Electrical characteristics 5.3.19 Communications interfaces I2C interface characteristics The STM32F415xx and STM32F417xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 52. Characteristics of TIMx connected to the APB2 domain(1) 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz 1- tTIMxCLK 5.95 - ns AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz 1- tTIMxCLK 11.9 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 168 MHz APB2 = 84 MHz 0fTIMxCLK/2 MHz 084 MHz ResTIM Timer resolution - 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK tMAX_COUNT Maximum possible count - 32768 tTIMxCLK Table 53. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - µs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) -0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 |
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