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EvaluationBoard Scheda tecnica(PDF) 2 Page - Intersil Corporation |
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EvaluationBoard Scheda tecnica(HTML) 2 Page - Intersil Corporation |
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2 / 16 page ![]() ISL75052SEH 2 FN8456.0 May 29, 2013 Block Diagram REFERENCE BIAS UVLO CURRENT LIMIT THERMAL SHUTDOWN DELAY GND PG ADJ EN VIN POWER PDMOS VOUT COMP BYP 3.8V LDO VCCX OCP 540mV 600mV Typical Applications FIGURE 3. PG 4.87k 15.8k 2.2k VCCX 10k EN VIN 1nF 22k 1 3 2 ISL75052SEH 16 15 14 13 12 11 10 9 4 5 6 7 8 BYP VOUT VOUT VIN VIN VIN NC NC OCP ADJ EN GND GND COMP PG VCCX NC = No connect pin can be connected to either VIN or GND VOUT = 2.5V 300 0.1µF 100µF 100µF 0.1µF 100µF 0.1µF 100µF Ω 2.2nF |
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