PIC16F1946 datasheet(302/478 Pages) MICROCHIP

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PIC16(L)F1946/47

DS41414D-page 302

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25.1.2

EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown

in Figure 25-2. The data is received on the RXx/DTx

pin and drives the data recovery block. The data

recovery block is actually a high-speed shifter

operating at 16 times the baud rate, whereas the serial

Receive Shift Register (RSR) operates at the bit rate.

When all 8 or 9 bits of the character have been shifted

in, they are immediately transferred to a two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCxREG

25.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCxSTA register enables

the receiver circuitry of the EUSART. Clearing the SYNC

bit of the TXxSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCxSTA

enables

the

EUSART.

The

programmer must set the corresponding TRIS bit to

configure the RXx/DTx I/O pin as an input.

If the RXx/DTx pin is shared with an analog peripheral

the analog I/O function must be disabled by clearing the

corresponding ANSEL bit.

25.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 25.1.2.5 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCxIF interrupt

flag bit of the PIR1/PIR3 register is set. The top charac-

ter in the FIFO is transferred out of the FIFO by reading

the RCxREG register.

25.1.2.3

Receive Data Polarity

The polarity of the receive data can be controlled with

the DTRXP bit of the BAUDxCON register. The default

state of this bit is ‘0’ which selects high true receive idle

and data bits. Setting the DTRXP bit to ‘1’ will invert the

receive data resulting in low true idle and data bits. The

DTRXP bit controls receive data polarity only in

Asynchronous mode. In synchronous mode the

DTRXP bit has a different function.

Note 1:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 25.1.2.6

“Receive Overrun Error” for more

information on overrun errors.

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