A32100DX datasheet(13/98 Pages) ACTEL

13 / 98 page

Hi R e l F P GA s

Fi x ed Capa ci t anc e V a l u es for

Act e l FP GA s (pF)

Fi x ed Cl o ck Loads ( s 1/s 2—A CT 3 Only)

De te r m i n i n g Av er age S w i tc h i n g Fr equ ency

To determine the switching frequency for a design, you must

have a detailed understanding of the data values input to the

circuit. The guidelines in the table below are meant to

represent worst-case scenarios so that they can be generally

used to predict the upper limits of power dissipation.

Device Type

routed_Clk1

routed_Clk2

A1010B

n/a

A1020B

n/a

A1240A

134

A1280A

168

A1280XL

168

A1425A

A1460A

165

A14100A

195

A32100DX

178

A32200DX

230

Device Type

Clock Loads on

Dedicated

Array Clock

Clock Loads on

Dedicated

I/O Clock

A1425A

160

100

A1460A

432

168

A14100A

697

228

Type

ACT 3

3200DX/ACT 2/1200XL

ACT 1

Logic modules (m)

80% of modules

90% of modules

Input switching (n)

# inputs/4

Outputs switching (p)

#outputs/4

First routed array clock loads (q1)

40% of sequential

modules

40% of sequential

modules

40% of modules

Second routed array clock loads (q2)

40% of sequential

modules

40% of sequential

modules

n/a

Load capacitance (CL)

35 pF

Average logic module switching rate (fm)

F/10

Average input switching rate (fn)

F/5

Average output switching rate (fp)

F/10

Average first routed array clock rate (fq1)F/2

Average second routed array clock rate (fq2)

F/2

n/a

Average dedicated array clock rate (fs1)F

n/a

Average dedicated I/O clock rate (fs2)F

n/a

A32100DX Scheda tecnica(PDF) 13 Page - Actel Corporation

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