LAN8710AI datasheet(72/82 Pages) SMSC

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Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

Datasheet

Revision 1.4 (08-23-12)

SMSC LAN8710A/LAN8710Ai

DATASHEET

5.5.3

Power-On nRST & Configuration Strap Timing

This diagram illustrates the nRST reset and configuration strap timing requirements in relation to

power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation,

nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must

not be deasserted before tpurstd after all external power supplies have reached 80% of their nominal

operating levels. In order for valid configuration strap values to be read at power-up, the tcss and tcsh

timing constraints must be followed. Refer to Section 3.8.5, "Resets," on page 41 for additional

information.

Note: nRST deassertion must be monotonic.

Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,

"Configuration Straps," on page 36 for details. Configuration straps must only be pulled high or

low and must not be driven as inputs.

Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.

Figure 5.3 Power-On nRST & Configuration Strap Timing

Table 5.7 Power-On nRST & Configuration Strap Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tpurstd

External power supplies at 80% to nRST deassertion

tpurstv

External power supplies at 80% to nRST valid

trstia

nRST input assertion time

100

μS

tcss

Configuration strap pins setup to nRST deassertion

200

tcsh

Configuration strap pins hold after nRST deassertion

totaa

Output tri-state after nRST assertion

todad

Output drive after nRST deassertion

800

(Note 5.14)

tcss

nRST

Configuration Strap

Pins Input

trstia

tcsh

Configuration Strap

Pins Output Drive

todad

All External

Power Supplies

tpurstd

80%

tpurstv

totaa

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