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MPC823 Scheda tecnica(PDF) 57 Page - Freescale Semiconductor, Inc |
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MPC823 Scheda tecnica(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 70 page  MPC823 ELECTRICAL SPECIFICATIONS 57 Table 16. Serial Peripheral Interface Master Timing NUM CHARACTERISTIC 25MHZ 40MHZ 50MHZ UNIT MIN MAX MIN MAX MIN MAX 160 Master cycle time 4 1,024 4 1,024 4 1,024 tcyc 161 Master clock (SCK) high or low time 2 512 2 512 2 512 tcyc 162 Master data setup time (inputs) 50 Ñ 50 Ñ 50 Ñ ns 163 Master data hold time (inputs) 0Ñ0Ñ0Ñ ns 164 Master data valid (after SCK edge) Ñ 20 Ñ 20 Ñ 20 ns 165 Master data hold time (outputs) 0Ñ0Ñ0Ñ ns 166 Rise time output Ñ 15 Ñ 15 Ñ 15 ns 167 Fall time output Ñ 15 Ñ 15 Ñ 15 ns NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1. Figure 52. SPI Master (CP=0) Timing Diagram SPICLK CI=0 (OUTPUT) SPICLK CI=1 (OUTPUT) SPIMISO (INPUT) SPIMOSI (OUTPUT) MSBIN DATA LSBIN MSBIN MSBOUT DATA LSBOUT MSBOUT 161 161 160 166 167 166 167 163 162 165 164 166 167 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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