MC68331MFC20 datasheet(27/84 Pages) FREESCALE

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MC68331TS/D

For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,

the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.

The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the

DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns

DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word

operation.

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular

port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data

bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the

MCU transfers valid data.

The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-

ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-

nated as shown in the following figure. OP0 is the most significant byte of a long-word operand, and

OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and

OP1. The single byte of a byte-length operand is OP0.

Figure 8 Operand Byte Order

3.4.10 Operand Alignment

The data multiplexer establishes the necessary connections for different combinations of address and

data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-

sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the

remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-

ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.

ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in-

dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the

byte offset from the base.

3.4.11 Misaligned Operands

CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it

overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-

dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address

is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is

misaligned at an odd address. MC68300 devices do not support misaligned operand transfers.

The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU

transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the

first bus cycle and the least significant operand word on a following bus cycle.

3.4.12 Operand Transfer Cases

The following table summarizes how operands are aligned for various types of transfers. OPn entries

are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,

SIZ0, and ADDR0 for that bus cycle.

Operand

Byte Order

Long Word

OP0

OP1

OP2

OP3

Three Byte

OP0

OP1

OP2

Word

OP0

OP1

Byte

OP0

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