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CC1150-RTR1 Scheda tecnica(PDF) 29 Page - Texas Instruments |
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CC1150-RTR1 Scheda tecnica(HTML) 29 Page - Texas Instruments |
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29 / 67 page  CC1150 SWRS037A Page 29 of 60 the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a CC1101. When FEC and interleaving is used, the minimum data payload is 2 bytes in fixed and variable packet length mode. Packet Engine FEC Encoder Modulator Interleaver Write buffer Interleaver Read buffer Demodulator FEC Decoder Packet Engine Interleaver Write buffer Interleaver Read buffer Figure 15: General Principle of Matrix Interleaving |
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