5

IXDD504 / IXDE504

SYMBOL

FUNCTION

DESCRIPTION

EN A

A Channel Enable

Channel A enable pin. When driven low, this pin disables the A channel and

forces a high impedance state to the A channel output.

IN A

A Channel Input

A channel input signal-TTL or CMOS compatible.

GND

Ground

The system ground pin. Internally connected to all circuitry, this pin provides

ground reference for the entire chip. This pin should be connected to a low

noise analog ground plane for optimum performance.

IN B

B Channel Input

B channel input signal-TTL or CMOS compatible.

OUT B

B Channel Output

B channel driver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

VCC

Supply Voltage

Positive power-supply voltage input. This pin provides power to the entire

chip. The range for this voltage is from 4.5V to 30V.

OUT A

A Channel Output

A channel driver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

EN B

B Channel Enable

Channel B enable pin. When driven low, this pin disables the B channel and

forces a high impedance state to the B channel output.

Pin Description

Figure 3 - Characteristics Test Diagram

CAUTION: Follow proper ESD procedures when handling and assembling this component.

IXYS reserves the right to change limits, test conditions, and dimensions.

NOTE: Solder tabs on bottoms of DFN packages are grounded

8 PIN DIP (PI)

8 PIN SOIC (SIA)

EN A

IN A

GND

IN B

EN B

OUT A

OUT B

VCC

1

2

3

4

8

7

6

5

I

X

D

D

5

0

4

8 LEAD DFN (D2)

(Bottom View)

EN A

IN A

IN B

EN B

OUT A

GND

OUT B

VCC

1

2

3

4

8

7

6

5

I

X

D

D

5

0

4

8 PIN DIP (PI)

8 PIN SOIC (SIA)

EN A

IN A

GND

IN B

EN B

OUT A

OUT B

VCC

1

2

3

4

8

7

6

5

I

X

D

E

5

0

4

8 LEAD DFN (D2)

(Bottom View)

EN A

IN A

IN B

EN B

OUT A

GND

OUT B

VCC

1

2

3

4

8

7

6

5

I

X

D

E

5

0

4

Pin Configurations