STM32F101ZF datasheet(89/108 Pages) STMICROELECTRONICS

89 / 108 page

STM32F101xF, STM32F101xG

Electrical characteristics

Doc ID 17143 Rev 2

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions

summarized in Table 10.

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO).

Table 53.

STM32F10xxx SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and

fall time

Capacitive load: C = 30 pF

tsu(NSS)

(1)

Based on characterization, not tested in production.

NSS setup time

Slave mode

4tPCLK

th(NSS)

(1)

NSS hold time

Slave mode

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low

time

Master mode, fPCLK = 36 MHz,

presc = 4

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup

time

Master mode - SPI1

Master mode - SPI2

Slave mode

th(MI)

(1)

Data input hold time

Master mode - SPI1

Master mode - SPI2

th(SI)

(1)

Slave mode

ta(SO)

(1)(2)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Data output access

time

Slave mode, fPCLK = 36 MHz,

presc = 4

055

Slave mode, fPCLK = 20 MHz

4tPCLK

tdis(SO)

(1)(3)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Data output disable

time

Slave mode

tv(SO)

(1)

Data output valid

time

Slave mode (after enable edge)

tv(MO)

(1)

Data output valid

time

Master mode (after enable edge)

th(SO)

(1)

Data output hold

time

Slave mode (after enable edge)

th(MO)

(1)

Master mode (after enable edge)

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