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CY3663 Scheda tecnica(PDF) 13 Page - Cypress Semiconductor

Il numero della parte CY3663
Spiegazioni elettronici  EZ-OTG??Programmable USB On-The-Go Host/Peripheral Controller
PDF  92 Pages
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY3663 Scheda tecnica(HTML) 13 Page - Cypress Semiconductor

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CY7C67200
Document Number: 38-08014 Rev. *I
Page 13 of 92
Bank Register [0xC002] [R/W]
Figure 8. Bank Register
Register Description
The Bank register maps registers R0–R15 into RAM. The eleven
MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
1. Shifting the four LSBs of the register address left by 1
2. ORing the four shifted bits of the register address with the 12
MSBs of the Bank Register
3. Forcing the LSB to zero
For example, if the Bank register is left at its default value of
0x0100, and R2 is read, then the physical address 0x0102 will
be read. See Table 17 for details.
.
Address (Bits [15:4])
The Address field is used as a base address for all register
addresses to start from.
Reserved
All reserved bits must be written as ‘0’.
Hardware Revision Register [0xC004] [R]
Figure 9. Revision Register
Register Description
The Hardware Revision register is a read-only register that
indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number is increased by one for
each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Reserved
Read/Write
R/W
R/W
R/W
–
–
–
–
–
Default
0
0
0
X
X
X
X
X
Table 17. Bank Register Example
Register
Hex Value
Binary Value
Bank
0x0100
0000 0001 0000 0000
R14
0x000E << 1 = 0x001C
0000 0000 0001 1100
RAM
Location
0x011C
0000 0001 0001 1100
Bit #
15
14
13
12
11
10
9
8
Field
Revision...
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Revision
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X



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