M3062LFGPFP datasheet(52/103 Pages) RENESAS

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M16C/62P Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics

Rev.2.41

Jan 10, 2006

Page 50 of 96

REJ03B0001-0241

VCC1=VCC2=5V

Timing Requirements

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr =

−20 to 85°C / −40 to 85°C unless otherwise specified)

NOTES:

1. The condition is VCC1=VCC2=3.0 to 5.0V.

NOTES:

1. Calculated according to the BCLK frequency as follows:

2. Calculated according to the BCLK frequency as follows:

n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

n is “2” for 2-wait setting, “3” for 3-wait setting.

Table 5.13

External Clock Input (XIN input) (1)

Symbol

Parameter

Standard

Unit

Min.

Max.

External Clock Input Cycle Time

62.5

tw(H)

External Clock Input HIGH Pulse Width

tw(L)

External Clock Input LOW Pulse Width

External Clock Rise Time

External Clock Fall Time

Table 5.14

Memory Expansion Mode and Microprocessor Mode

Symbol

Parameter

Standard

Unit

Min.

Max.

tac1(RD-DB)

Data Input Access Time (for setting with no wait)

(NOTE 1)

tac2(RD-DB)

Data Input Access Time (for setting with wait)

(NOTE 2)

tac3(RD-DB)

Data Input Access Time (when accessing multiplex bus area)

(NOTE 3)

tsu(DB-RD)

Data Input Setup Time

tsu(RDY-BCLK)

RDY Input Setup Time

tsu(HOLD-BCLK) HOLD Input Setup Time

th(RD-DB)

Data Input Hold Time

th(BCLK-RDY)

RDY Input Hold Time

th(BCLK-HOLD)

HOLD Input Hold Time

0.5x10

fBCLK

()

------------------------45 ns

[]

–

n0.5

–

()x10

fBCLK

()

-------------------------------------45 ns

[]

–

n0.5

–

()x10

fBCLK

()

-------------------------------------45 ns

[]

–

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