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MMPF0100NPEP Scheda tecnica(PDF) 18 Page - Freescale Semiconductor, Inc |
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MMPF0100NPEP Scheda tecnica(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 137 page ![]() Analog Integrated Circuit Device Data 18 Freescale Semiconductor PF0100 Functional Block Requirements and Behaviors Start-up 6 Functional Block Requirements and Behaviors 6.1 Start-up The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kohm resistor. The OTP configuration is enabled by connecting VDDOTP to GND. For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled through the I2C port for prototyping and programming. Once programmed, the NP device will startup with the customer programmed configuration. 6.1.1 Device Start-up Configuration Table 8 shows the Default Configuration which can be accessed on all devices as described above, as well as the pre- programmed OTP configurations. Table 8. Start-up Configuration Registers Default Configuration Pre-programmed OTP Configuration All Devices F0 F1 F2 Default I2C Address 0x08 0x08 0x08 0x08 VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V SW1AB_SEQ 1 1 1 1 SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V SW1C_SEQ 1 2 1 1 SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V SW2_SEQ 2 5 2 2 SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V SW3A_SEQ 3 3 4 4 SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V SW3B_SEQ 3 3 4 4 SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V SW4_SEQ 3 6 3 3 SWBST_VOLT - 5.0 V 5.0 V 5.0 V SWBST_SEQ - 13 6 6 VREFDDR_SEQ 3 3 4 4 VGEN1_VOLT - 1.5 V 1.2 V 1.2 V VGEN1_SEQ - 9 4 4 VGEN2_VOLT 1.5 V 1.5 V - - VGEN2_SEQ 2 10 - - VGEN3_VOLT - 2.5 V - - VGEN3_SEQ - 11 - - VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V |
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