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JS28F256P30B95A Scheda tecnica(PDF) 46 Page - Micron Technology

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P30
Datasheet
August 2008
46
306666-12
11.2.6
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 22 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
11.2.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Table 22: Burst Sequence Word Ordering
Start
Addr.
(DEC)
Burst
Wrap
(RCR[3])
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] =
0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
0
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5…15-0
1-2-3-4-5-6-7-…
2
0
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6…15-0-1
2-3-4-5-6-7-8-…
3
0
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7…15-0-1-2
3-4-5-6-7-8-9-…
40
4-5-6-7-0-1-2-3
4-5-6-7-8…15-0-1-2-3
4-5-6-7-8-9-10…
50
5-6-7-0-1-2-3-4
5-6-7-8-9…15-0-1-2-3-4
5-6-7-8-9-10-11…
60
6-7-0-1-2-3-4-5
6-7-8-9-10…15-0-1-2-3-4-
5
6-7-8-9-10-11-12-…
70
7-0-1-2-3-4-5-6
7-8-9-10…15-0-1-2-3-4-5-
6
7-8-9-10-11-12-13…
14
0
14-15-0-1-2…12-13
14-15-16-17-18-19-20-…
15
0
15-0-1-2-3…13-14
15-16-17-18-19-20-21-…
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5…15-16
1-2-3-4-5-6-7-…
2
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6…16-17
2-3-4-5-6-7-8-…
3
1
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7…17-18
3-4-5-6-7-8-9-…
41
4-5-6-7-8-9-10-11
4-5-6-7-8…18-19
4-5-6-7-8-9-10…
51
5-6-7-8-9-10-11-12
5-6-7-8-9…19-20
5-6-7-8-9-10-11…
61
6-7-8-9-10-11-12-13
6-7-8-9-10…20-21
6-7-8-9-10-11-12-…
71
7-8-9-10-11-12-13-
14
7-8-9-10-11…21-22
7-8-9-10-11-12-13…
14
1
14-15-16-17-18…28-29
14-15-16-17-18-19-20-…
15
1
15-16-17-18-19…29-30
15-16-17-18-19-20-21-…



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