STLUX385ATR datasheet(31/99 Pages) STMICROELECTRONICS

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STLUX385A

I/O multifunction signal configuration

The port P0[5:3] or P0[2:0] can be configured to output one or two different SMEDs’ current

state.

5.2.3

Port P0 I/O functional multiplexing signal

Figure 7 shows an outline view of port P0 multi-function multiplexing scheme.

Figure 7. Port P0 I/O functional multiplexing scheme

Note:

Where “A/F(s) in” and “A/F(s) out” signals are defined in Section 4.2.

5.2.4

P0 programmable pull-up and speed feature

The I/O speed and pad pull-up resistance (47 k

Ω) of Port P0 may be configured through the

GPIO0 internal registers.

5.3

Port P1 I/O multifunction configuration signal

The Port1 I/O multifunction pins, similarly to Port0, can be individually configured through

the following set of registers based on the selected device configuration policy:

•

Cold configuration: AFR_IOMXP1 option byte register (refer to

Section 8). After reset

the P1 signals are configured in line with AFR_IOMXP1 contents.

•

Warm configuration: MISC_IOMXP1 miscellaneous register (refer to

Section 5.5). After

reset the P1 signals are configured as PWM output lines.

Every Port1 I/O can be configured to operate as a PWM output pin or a GPIO. Differently

from port P0s, the pins are configured as PWM output signals by default after reset.

The next table summarizes the port P1 configurations as selected by the register fields

Sel_p15…Sel_p10 which respectively control the bits [5]…[0] of port P1.

INPUT

OUTPUT

A/F(s) out

P0_IDR[5:0]

P0_ODR[5:0]

A/F IN

-MSC_IOMXP0

-AFR_IOMXP0

A/F(s) in

A/F OUT

P0[5:0]

GIPC080520131629FSR

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