ADXL375 datasheet(27/32 Pages) AD

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Data Sheet

ADXL375

Rev. 0 | Page 27 of 32

Several events invalidate the second shock of a double shock event.

•

If the suppress bit in the SHOCK_AXES register (Bit D3,

Address 0x2A) is set, any acceleration spike above the

threshold during the latency time (set by the latent register)

invalidates the double shock detection (see Figure 34).

INVALIDATES DOUBLE SHOCK IF

SUPPRESS BIT SET

TIME WINDOW FOR SECOND

SHOCK (WINDOW)

LATENCY

TIME (LATENT)

TIME LIMIT

FOR SHOCKS

(DUR)

Figure 34. Double Shock Event Invalid Due to High g Event

When the Suppress Bit Is Set

•

A double shock event can be invalidated if acceleration

above the threshold is detected at the start of the time

window for the second shock (set by the window register),

resulting in an invalid double shock at the start of this

window (see Figure 35).

•

A double shock event can be invalidated if acceleration

exceeds the time limit for shocks (set by the DUR register),

resulting in an invalid double shock at the end of the DUR

time limit for the second shock event (see Figure 35).

INVALIDATES DOUBLE SHOCK

AT START OF WINDOW

TIME WINDOW FOR

SECOND SHOCK (WINDOW)

LATENCY

TIME

(LATENT)

INVALIDATES

DOUBLE SHOCK AT

END OF DUR

TIME LIMIT

FOR SHOCKS

(DUR)

TIME LIMIT

FOR SHOCKS

(DUR)

TIME LIMIT

FOR SHOCKS

(DUR)

Figure 35. Shock Interrupt Function with Invalid Double Shocks

Single shocks, double shocks, or both can be detected by setting

the appropriate bits in the INT_ENABLE register (Address 0x2E).

Participation of each of the three axes in single shock/double

shock detection is controlled by setting the appropriate bits in

the SHOCK_AXES register (Address 0x2A). For the double

shock function to operate, both the latent and window registers

must be set to a nonzero value.

Every mechanical system has somewhat different shock responses

based on the mechanical characteristics of the system. Therefore,

some experimentation with values for the DUR, latent, window,

and THRESH_SHOCK registers is required.

Setting a very low value in the latent, window, or THRESH_

SHOCK register can result in unpredictable responses due to

the accelerometer picking up echoes of the shock inputs.

After a shock interrupt is received, the first axis to exceed the

THRESH_SHOCK level is reported in the ACT_SHOCK_

STATUS register (Address 0x2B). This register is never cleared

but is overwritten with new data.

THRESHOLD DETECTION AND BANDWIDTH

Lower output data rates are achieved by decimating a common

sampling frequency inside the device. The activity and single

shock/double shock detection functions are performed using

undecimated data. Because the bandwidth of the output data

varies with the data rate and is lower than the bandwidth of the

undecimated data, the high frequency and high g data that is used

to determine activity and single shock/double shock events may

not be present if the output of the accelerometer is examined. This

may result in the triggering of these functions when acceleration

data does not appear to meet the conditions set by the user for

the corresponding function.

LINK MODE

The link bit (Bit D5) in the POWER_CTL register (Address 0x2D)

can be used to reduce the number of activity interrupts that the

processor must service. The link bit configures the device to look

for activity only after inactivity.

For proper operation of this feature, the processor must still

respond to the activity and inactivity interrupts by reading the

INT_SOURCE register (Address 0x30) and, therefore, clearing

the interrupts. If an activity interrupt is not cleared, the part

cannot enter autosleep mode. The asleep bit (Bit D3) in the

ACT_SHOCK_STATUS register (Address 0x2B) indicates

whether the part is asleep.

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