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PIC18F2525IP Scheda tecnica(PDF) 119 Page - Microchip Technology |
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PIC18F2525IP Scheda tecnica(HTML) 119 Page - Microchip Technology |
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119 / 412 page ![]() © 2008 Microchip Technology Inc. DS39626E-page 117 PIC18F2525/2620/4525/4620 REGISTER 10-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled |
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