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AD5227BUJZ50-R2 Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD5227BUJZ50-R2 Scheda tecnica(HTML) 6 Page - Analog Devices |
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6 / 16 page ![]() AD5227 Rev. B | Page 6 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5227 TOP VIEW (Not to Scale) CLK 1 U/D 2 A 3 GND 4 VDD CS B W 8 7 6 5 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined by the state of the U/D pin. CLK is a negative-edge trigger. Logic high signal can be higher than VDD, but lower than 5.5 V. 2 U/D Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than VDD, but lower than 5.5 V. 3 A Resistor Terminal A. GND ≤ VA ≤ VDD. 4 GND Common Ground. 5 W Wiper Terminal W. GND ≤ VW ≤ VDD. 6 B Resistor Terminal B. GND ≤ VB ≤ VDD. 7 CS Chip Select. Active Low. Logic high signal can be higher than VDD, but lower than 5.5 V. 8 VDD Positive Power Supply, 2.7 V to 5.5 V. |
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