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AZP53 Scheda tecnica(PDF) 4 Page - Arizona Microtek, Inc

Il numero della parte AZP53
Spiegazioni elettronici  Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator
PDF  13 Pages
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Produttore elettronici  AZM [Arizona Microtek, Inc]
Homepage  http://azmicrotek.com
Logo AZM - Arizona Microtek, Inc

AZP53 Scheda tecnica(HTML) 4 Page - Arizona Microtek, Inc

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Arizona Microtek, Inc.
AZP53
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
www.azmicrotek.com
+1-480-962-5881
4
Request a Sample
Mar 2013, Rev 2.2
Figure 2- S11, Parameters, D Input
INPUT TERMINATION
The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mVpp ensures the AZP53 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.
D
VDD/2
10k
Ω
Input signal
A/R
Figure 3 - Input Termination



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