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H5TC4G43AFR-RDA Scheda tecnica(PDF) 22 Page - Hynix Semiconductor

Il numero della parte H5TC4G43AFR-RDA
Spiegazioni elettronici  4Gb DDR3L SDRAM
PDF  35 Pages
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Produttore elettronici  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5TC4G43AFR-RDA Scheda tecnica(HTML) 22 Page - Hynix Semiconductor

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Rev. 1.0 / Apr. 2013
22
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Datab)
0
0
D1
0
0
0
0
0
0
0
0
0
0
-
1D
1
0
0
0
0
0
0
0
0
0
0
-
2D
11
1
1
0
0
0
0
0
F
0
-
3D
11
1
1
0
0
0
0
0
F
0
-
1 4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
Datab)
0
0
D1
0
0
0
0
0
0
0
0
0
0
-
1D
1
0
0
0
0
0
0
0
0
0
0
-
2D
11
1
1
0
0
0
0
0
F
0
-
3D
11
1
1
0
0
0
0
0
F
0
-
1 4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7



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