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H5TQ4G43AFR-RDC Scheda tecnica(PDF) 32 Page - Hynix Semiconductor |
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H5TQ4G43AFR-RDC Scheda tecnica(HTML) 32 Page - Hynix Semiconductor |
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32 / 35 page ![]() Rev. 1.0 / Apr. 2013 32 DDR3-2133 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-2133N Unit Note CL - nRCD - nRP 14-14-14 Parameter Symbol min max Internal read command to first data tAA 13.90 20.0 ns ACT to internal read or write delay time tRCD 13.90 — ns PRE command period tRP 13.90 — ns ACT to PRE command period tRAS 33.0 9 * tREFI ns ACT to ACT or PRE command period tRC 46.09 - ns CL = 5 CWL = 5 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 6,7,8,9,10 tCK(AVG) Reserved ns 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1 2,3,10 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 7,8,9,10 tCK(AVG) Reserved ns 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,10 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 8,9,10 tCK(AVG) Reserved ns 4 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,10 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 8,9,10 tCK(AVG) Reserved ns 4 CL = 9 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,10 CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 9,10 tCK(AVG) Reserved ns 4 CL = 10 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,10 CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 9 tCK(AVG) Reserved ns 4 CWL = 10 tCK(AVG) Reserved ns 4 CL = 11 CWL = 5,6,7 tCK(AVG) Reserved ns 4 CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,10 CWL = 9 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 10 tCK(AVG) Reserved ns 1,2,3,4 CL = 12 CWL = 5,6,7,8 tCK(AVG) Reserved ns 4 CWL = 9 tCK(AVG) Reserved ns 1,2,3,4,10 CWL = 10 tCK(AVG) Reserved ns 4 CL = 13 CWL = 5,6,7,8 tCK(AVG) Reserved ns 4 CWL = 9 tCK(AVG) 1.07 <1.25 ns 1,2,3,10 CWL = 10 tCK(AVG) Reserved ns 1,2,3,4 CL = 14 CWL = 5,6,7,8,0 tCK(AVG) Reserved ns 4 CWL = 10 tCK(AVG) 0.935 <1.07 ns 1,2,3 Supported CL Settings 6, 7, 8, 9, 10, 11, 13, 14 nCK Supported CWL Settings 5, 6, 7, 8, 9, 10 nCK |
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