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ADSP-21486KSWZ-2AB Scheda tecnica(PDF) 54 Page - Analog Devices |
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ADSP-21486KSWZ-2AB Scheda tecnica(HTML) 54 Page - Analog Devices |
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54 / 68 page  Rev. B | Page 54 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 JTAG Test Access Port and Emulation Table 54. JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements tTCK TCK Period 20 ns tSTAP TDI, TMS Setup Before TCK High 5 ns tHTAP TDI, TMS Hold After TCK High 6 ns tSSYS 1 1 System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0. System Inputs Setup Before TCK High 7 ns tHSYS 1 System Inputs Hold After TCK High 18 ns tTRSTW TRST Pulse Width 4tCK ns Switching Characteristics tDTDO TDO Delay from TCK Low 10 ns tDSYS 2 2 System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU. System Outputs Delay After TCK Low tTCK ÷ 2 + 7 ns Figure 40. IEEE 1149.1 JTAG Test Access Port TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS tTCK tSTAP tHTAP tDTDO tSSYS tHSYS tDSYS |
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