CDPCLK2 datasheet(87/274 Pages) ALTERA

87 / 274 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–27

PLL Reconfiguration

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 5–20 shows how to adjust PLL counter settings dynamically by shifting their

new settings into a serial shift register chain or scan chain. Serial data shifts to the scan

chain via the scandataport, and shift registers are clocked by scanclk. The maximum

scanclk

frequency is 100 MHz. After shifting the last bit of data, asserting the

configupdate

signal for at least one scanclk clock cycle synchronously updates the

PLL configuration bits with the data in the scan registers.

1 The counter settings are updated synchronously to the clock frequency of the

individual counters. Therefore, not all counters update simultaneously.

To reconfigure the PLL counters, perform the following steps:

1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the

first bit of scandata (Dn).

2. Serial data (scandata) is shifted into the scan chain on the second rising edge of

scanclk

3. After all 144 bits have been scanned into the scan chain, the scanclkena signal is

deasserted to prevent inadvertent shifting of bits in the scan chain.

4. The configupdate signal is asserted for one scanclk cycle to update the PLL

counters with the contents of the scan chain.

5. The scandone signal goes high indicating that the PLL is being reconfigured. A

falling edge indicates that the PLL counters have been updated with new settings.

6. Reset the PLL using the areset signal if you make any changes to the M, N,

post-scale output C counters, or the ICP , R, C settings.

7. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.

Figure 5–20. PLL Reconfiguration Scan Chain

/C4

/C3

/C2

/C1

/C0

scanclk

scandone

scandata

LF/K/CP

configupdate

inclk

PFD

VCO

FVCO

scanclkena

scandataout

from M counter

from N counter

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