CDPCLK2 datasheet(117/274 Pages) ALTERA

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Chapter 6: I/O Features in the Cyclone III Device Family

6–19

I/O Banks

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Each I/O bank of the Cyclone III device family has its own VCCIO pins. Each I/O bank

can support only one VCCIO setting from among 1.2, 1.5, 1.8, 3.0, or 3.3 V. Any number

of supported single-ended or differential standards can be simultaneously supported

in a single I/O bank, as long as they use the same VCCIO levels for input and output

pins.

When designing LVTTL/LVCMOS inputs with Cyclone III and Cyclone III LS

devices, refer to the following guidelines:

■

All pins accept input voltage (VI) up to a maximum limit (3.6 V), as stated in the

recommended operating conditions are provided in the Cyclone III Device Data

Sheet and Cyclone III LS Device Data Sheet chapters.

■

Whenever the input level is higher than the bank VCCIO, expect higher leakage

current.

■

The LVTTL/LVCMOS I/O standard input pins can only meet the VIH and VIL

levels according to bank voltage level.

Voltage-referenced standards are supported in an I/O bank using any number of

single-ended or differential standards, as long as they use the same VREF and VCCIO

values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your

Cyclone III and Cyclone III LS devices, I/O pins using these standards—because they

require different VREF values—must be in different banks from each other. However,

the same I/O bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to

2.5 V and the VREF set to 1.25 V.

1 When using Cyclone III and Cyclone III LS devices as a receiver in 3.3-, 3.0-, or 2.5-V

LVTTL

/LVCMOS systems, you are responsible for managing overshoot or

undershoot to stay in the absolute maximum ratings and the recommended operating

conditions, provided in the Cyclone III Device Data Sheet and Cyclone III LS Device Data

Sheet chapters.

1 The PCI clamping diode is enabled by default in the Quartus II software for input

signals with bank VCCIO at 2.5, 3.0, or 3.3 V.

EP3CLS70

UBGA

278

333

FBGA

278

333

FBGA

413

333

EP3CLS100

UBGA

278

333

FBGA

278

333

FBGA

413

333

EP3CLS150

FBGA

210

333

FBGA

413

333

EP3CLS200

FBGA

210

333

FBGA

413

333

Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices

(Part 2 of 2)

Family

Device

Package

Pin Count

I/O Banks

345

678

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