CDPCLK5 datasheet(89/274 Pages) ALTERA

89 / 274 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–29

PLL Reconfiguration

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

■

High time count = 2 cycles

■

Low time count = 1 cycle

■ rselodd

= 1 effectively equals:

■

High time count = 1.5 cycles

■

Low time count = 1.5 cycles

■

Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count

Scan Chain Description

Cyclone III device family PLLs have a 144-bit scan chain.

Table 5–4 lists the number of bits for each component of the PLL.

Figure 5–22 shows the scan chain order of the PLL components.

Table 5–4. Cyclone III Device Family PLL Reprogramming Bits

Block Name

Number of Bits

Counter

Other

Total

C4 (1)

2 (2)

M16

2 (2)

N16

2 (2)

Charge Pump

Loop Filter (3)

Total number of bits:

144

Notes to Table 5–4:

(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.

(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty

cycle.

(3) MSB bit for loop filter is the last bit shifted into the scan chain.

Figure 5–22. PLL Component Scan Chain Order

DATAIN

DATAOUT

MSB

LSB

MC0

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