CDPCLK6 datasheet(33/274 Pages) ALTERA

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Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

2–7

Document Revision History

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 2–6 shows the LAB control signal generation circuit.

LAB-wide signals control the logic for the clear signal of the register. The LE directly

supports an asynchronous clear function. Each LAB supports up to two asynchronous

clear signals (labclr1 and labclr2).

A LAB-wide asynchronous load signal to control the logic for the preset signal of the

technique. The Cyclone III device family only supports either a preset or

asynchronous clear signal.

In addition to the clear port, the Cyclone III device family provides a chip-wide reset

pin (DEV_CLRn) that resets all registers in the device. An option set before compilation

in the Quartus II software controls this pin. This chip-wide reset overrides all other

control signals.

Document Revision History

Table 2–1 lists the revision history for this document.

Figure 2–6. Cyclone III Device Family LAB-Wide Control Signals

labclkena1

labclk2

labclk1

labclkena2

labclr1

Dedicated

LAB Row

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

syncload

synclr

labclr2

Table 2–1. Document Revision History (Part 1 of 2)

Date

Version

Changes

December 2011

2.3

Minor text edits.

December 2009

2.2

Minor changes to the text.

July 2009

2.1

Minor edit to the hyperlinks.

June 2009

2.0

Updated to include Cyclone III LS information

■ Updated chapter part number.

■ Updated “Introduction” on page 2–1.

■ Updated Figure 2–1 on page 2–2 and Figure 2–4 on page 2–5.

■ Updated “LAB Control Signals” on page 2–6.

October 2008

1.2

Updated chapter to new template.

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