MPC8349EVVALDB datasheet(24/87 Pages) FREESCALE

24 / 87 page

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.2.1.1

GMII Transmit AC Timing Specifications

Table 25 provides the GMII transmit AC timing specifications.

Figure 9 shows the GMII transmit AC timing diagram.

Figure 9. GMII Transmit AC Timing Diagram

8.2.1.2

GMII Receive AC Timing Specifications

Table 26 provides the GMII receive AC timing specifications.

Table 25. GMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

GTX_CLK clock period

tGTX

—8.0

—

GTX_CLK duty cycle

tGTXH/tGTX

43.75

—

56.25

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

tGTKHDX

0.5

—

5.0

GTX_CLK clock rise time (20%–80%)

tGTXR

——

1.0

GTX_CLK clock fall time (80%–20%)

tGTXF

——

1.0

Notes:

1. The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and

t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT)

with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the

valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock

reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general,

the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript

of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

Table 26. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

RX_CLK clock period

tGRX

—8.0

—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tGRDXKH

0.5

—

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

TX_EN

TX_ER

MPC8349EVVALDB Scheda tecnica(PDF) 24 Page - Freescale Semiconductor, Inc

MPC8349EVVALDB Scheda tecnica(HTML) 24 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Scheda tecnica Scarica

Link URL