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2

Block Diagrams

*Please look into Section 8, Appendix D for availability of various package types.

Truth Table

X

= Don’t Care

H

= V

IN(1)

L

= V

IN(0)

↑ = Clock transition from V

P0 thru P7

= Data present (and loaded into) parallel inputs

Q0 thru Q6

= Internal flip-flop outputs

State

Inputs

Internal

Outputs

PL

Clock1

Clock2

Ds

P0 thru P7

Q0

Q1

Q7

Q7

(as enable)

Parallel Load

L

X

X

X

P0…P7

P0P1P7

P7

Enable

H

L

L

X

X

P0P1P7

P7

Shift (with Ds)

H

↑

L

H

X

H

P0

P6

P6

Shift (with Ds)

H

↑

LL

X

L

H

P5

P5

Hold (Disable)

H

↑

HX

X

L

H

P5

P5