ADC0804LCWM datasheet(26/48 Pages) TI

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ADC0801, ADC0802

ADC0803, ADC0804, ADC0805

SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013

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There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of

the data bus slows down the response time, even though DC specifications are still met. For systems operating

with a relatively slow CPU clock frequency, more time is available in which to establish proper logic levels on the

bus and therefore higher capacitive loads can be driven (see typical characteristics curves).

At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states

(8080) or using clock extending circuits (6800).

Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be TRI-

STATE buffers (low power Schottky such as the DM74LS240 series is recommended) or special higher drive

current products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are

recommended.

Power Supplies

Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A

low inductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 µF or

greater are recommended. If an unregulated voltage is available in the system, a separate LM340LAZ-5.0, TO-

92, 5V voltage regu- lator for the converter (and other analog circuitry) will greatly reduce digital noise on the VCC

supply.

Wiring and Hook-Up Precautions

Standard digital wire wrap sockets are not satisfactory for breadboarding this A/D converter. Sockets on PC

boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible

from the analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and hum

pickup, therefore shielded leads may be necessary in many applications.

A single point analog ground that is separate from the logic ground points should be used. The power supply

bypass capacitor and the self-clocking capacitor (if used) should both be returned to digital ground. Any VREF/2

bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog

ground point. A test for proper grounding is to measure the zero error of the A/D converter. Zero errors in excess

of 1/4 LSB can usually be traced to improper board layout and wiring (see Zero Error for measuring the zero

error).

TESTING THE A/D CONVERTER

There are many degrees of complexity associated with test- ing an A/D converter. One of the simplest tests is to

apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as

shown in Figure 53.

For ease of testing, the VREF/2 (pin 9) should be supplied with 2.560 VDC and a VCC supply voltage of 5.12 VDC

should be used. This provides an LSB value of 20 mV.

If a full-scale adjustment is to be made, an analog input voltage of 5.090 VDC (5.120–1/⁄2 LSB) should be applied

to the VIN(+) pin with the VIN(−) pin grounded. The value of the VREF/2 input voltage should then be adjusted until

the digital output code is just changing from 1111 1110 to 1111 1111. This value of VREF/2 should then be used

for all the tests.

The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters, the 4 most significant

(MS) and the 4 least significant (LS). Table 2 shows the fractional binary equivalent of these two 4-bit groups. By

adding the voltages obtained from the "VM" and "VLS" columns in Table 2 , the nominal value of the digital

display (when VREF/2 = 2.560V) can be determined. For example, for an output LED display of 1011 0110 or B6

(in hex), the voltage values from the table are 3.520 + 0.120 or 3.640 VDC. These voltage values represent the

center-values of a perfect A/D converter. The effects of quantization error have to be accounted for in the

interpretation of the test results.

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