ADS1606IPAPT datasheet(10/38 Pages) TI

10 / 38 page

ADS1605

ADS1606

SBAS274H − MARCH 2003 − REVISED MAY 2007

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CLK

DRDY

DOUT[15:0]

DL(2)

CS(1)

(1) CS may be tied low.

(2) The number of data readings (DL) is set by the FIFO level.

Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled)

RD, CS

DOUT[15:0]

Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled)

TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

CLK period (1/fCLK)

1000

CLK pulse width, high or low

Rising edge of RD and/or CS inactive (high) to DOUT high impedance

Falling edge of RD and/or CS active (low) to DOUT active.

t13

Rising edge of CLK to DRDY high

t14

DRDY period

× FIFO Level(1)

CLK

Cycles

t15

DRDY positive pulse width

CLK

Cycles

t16

RD high hold time after DRDY goes low

t17

CS low before RD goes low

t18

RD negative pulse width

t19

RD positive pulse width

t20

RD high before DRDY toggles

CLK

Cycles

t21

RD high before CS goes high

NOTE: DOUT[15:0] and DRDY load = 10pF.

(1) See FIFO section for more details.

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