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74LVC07APW Scheda tecnica(PDF) 6 Page - NXP Semiconductors |
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74LVC07APW Scheda tecnica(HTML) 6 Page - NXP Semiconductors |
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6 / 14 page ![]() 74LVC07A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 27 October 2011 6 of 14 NXP Semiconductors 74LVC07A Hex buffer with open-drain outputs 11. Waveforms Measurements points are given in Table 8. Logic level: VOL is a typical output voltage level that occurs with the output load. Fig 6. The input (nA) to output (nY) propagation delays mna528 tPLZ VX nY output nA input VI VCC VM VM VOL GND tPZL VM Table 8. Measurement points Supply voltage Input Output VCC VM VX < 2.7 V 0.5 V CC VOL +0.15 V 2.7 V to 3.6 V 1.5 V VOL +0.3 V 4.5 V to 5.5 V 0.5 V CC VOL +0.3 V |
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