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VN06 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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VN06 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
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8 / 17 page ![]() Electrical specifications VN06 8/17 Table 6. Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Input low level voltage 0.8 V VIH (1) 1. The VIH is internally clamped at 6V about. It is possible to connect this pin to an higher voltage via an external resistor calculated to not exceed 10 mA at the input pin. Input high level voltage 2 V VI(hyst.) Input hysteresis voltage 0.5 V IIN Input current VIN = 5 V VIN = 2 V VIN = 0.8 V 25 250 500 250 µA µA µA VICL Input clamp voltage IIN = 10 mA IIN = -10 mA 5.5 6 -0.7 -0.3 V V Table 7. Protections and diagnostics Symbol Parameter Test conditions Min. Typ. Max. Unit VSTAT Status voltage output low ISTAT = 1.6 mA 0.4 V VUSD Under voltage shutdown 5 V VSCL Status clamp voltage ISTAT = 10 mA ISTAT = -10 mA 6 -0.7 V V IOV Over current RLOAD < 10 mΩ -40 ≤Tc ≤125 °C 60 A IAV Average current in short circuit RLOAD < 10 mΩ; Tc= 85 °C 1.4 A IOL Open load current level 5 80 180 mA TTSD Thermal shutdown temperature 140 °C TR Reset temperature 125 °C VOL (1) 1. IOL(off) = (VCC -VOL)/ROL. Open load voltage level Off state (see Figure 4.) 2.5 3.75 5 V t1(on) (2) 2. t1(on): minimum open load duration which acctivates the status output Open load filtering time 1 5 10 ms t1(off) (3) 3. t1(off): minimum load recovery time which desactivates the status output Open load filtering time 1 5 10 ms t2(off) (4) 4. t2(off): minimum on time after thermal shut down which desactivates status output Open load filtering time 1 5 10 ms tpovl (5) 5. tpovl tpol: ISO definition (see figure) Status delay (see Figure 5.) 5 10 µs tpol (5) Status delay (see Figure 5.) 50 700 µs |
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