AD5280 datasheet(15/28 Pages) AD

15 / 28 page

AD5280/AD5282

Rev. C | Page 15 of

input voltage applied to Terminal A and Terminal B is

()

256

256 −

()

(3)

For a more accurate calculation that includes the effect of wiper

resistance, VW can be found as

()

(4)

Operation of the digital potentiometer in divider mode results

in a more accurate operation over temperature. Unlike rheostat

mode, the output voltage is dependent mainly on the ratio of

the internal resistors RWA and RWB and not on the absolute

values; therefore, the temperature drift reduces to 5 ppm/°C.

SCL

SDA

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

ACK. BY

AD5280/5282

FRAME 2

INSTRUCTION BYTE

ACK. BY

AD5280/AD5282

FRAME 3

DATA BYTE

ACK. BY

AD5280/5282

STOP BY

MASTER

11 AD1

R/W

A/B

D6D5D4D3D2D1D0

AD0

Figure 45. Writing to the RDAC Register

SCL

SDA

ACK. BY

AD5280/AD5282

NO ACK. BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

DATA BYTE FROM PREVIOUSLY SELECTED

STOP BY

MASTER

AD1 AD0 R/W

D7D6D5D4D3D2

D1D0

Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode

Table 6. Serial Format of Data Accepted from the I2C Bus

AD1

A/B

X X

Slave Address Byte

Instruction Byte

Data Byte

where:

Abbreviation

Equals

Start condition

Stop condition

Acknowledge

Don’t care

AD1, AD0

Package pin programmable address bits

R/W

Read enable at high and write enable at low

A/B

RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2

Midscale reset, active high (only affects selected channel)

Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel)

O , O

Output logic pin latched values; default Logic 0

D7, D6, D5, D4, D3, D2, D1, D0

Data bits

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